SmartDv develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP's are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
asureVIP™ is a highly flexible and configurable verification portfolio which can be easily integrated into any complex digital SOC verification environment. Written natively in System Verilog or the e language for optimum performance, all of our VIP components are OVM/UVM or eRM compliant and can be provided as source code under our Flexible Licensing Model.