UVVM (Universal VHDL Verification Methodology) is the world-wide #1 VHDL Verification methodology and library. This is due to the improvement UVVM yields in both FPGA quality and development time. This open source Library and Methodology has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner providing modularity, reusability, constrained-random stimulus and functional coverage similar to UVM. UVVM also has the largest library of open source VHDL verification models and components. With more than 50% of all FPGA designers using VHDL, UVVM provides a great verification solution for these users. Thus, this free online webinar provided the attendees an introduction to UVVM so that they can start using it on their next or current projects.

The webinar was delivered by Espen TALLAKSEN, the CEO of EmLogic in Norway and also the author and architect of UVVM, the leading verification methodology and library for VHDL. Espen answered the questions of attendees at the end of the webinar.

Those who couldn’t attend the webinar online can watch the webinar recording from the link that will be sent to them by e-mail after completing the registration form on this link.