AES IP Cores is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in ”FIPS 197”. This standard specifies the Rijndael algorithm, a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits.

Countermeasures against side-channel attacks (DPA) are implemented in the AES IP Core. AES IP Core is compatible with Xilinx FPGAs and Intel FPGAs. VHDL is used as the Hardware Description Language of the IP Core. ECB, CBC, CTR, and GCM mode of operations are supported and implemented according to ”NIST SP800-38a” and ”NIST SP800-38d”. 

FEATURES LIST

AES IP Core:

• supports encryption and decryption for modes listed below:

                   •    ECB, CBC, CTR mode of operations
                   •    optional support for GCM

• supports 128, 192 and 256-bit key lengths
• Side-channel protected (PCI v4.0 certified) and unprotected options are available
• is compliant with FIPS 197
• is tested on Xilinx Z-7015 Z-7020 Z-7045 FPGAs
• has fully scalable input and output interfaces

DELIVERABLES

• Encrypted Netlist
• Synthesis Scripts
• Comprehensive Documentation 
• AES Validation Suite Testbenches in System Verilog

LICENSING

IP can be licensed as;

• Single project license
• Multi-project license

Delivery type of the IP can be;

• Encrypted Netlist
• Encrypted RTL

MAINTENANCE & SUPPORT

First-year M&S is mandatory. Customers receive IP updates and phone and email support related to the IP core under the M&S agreement.
 

ORDERING
Purchase order shall include the product number EIP-15009.
 

For more information, contact sales@electraic.com 

DOCUMENTS

AES IP Core Datasheet

Crypto IP Cores - Feature List Table