SmartDv develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). SmartDV verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. SmartDV currently supports SystemVerilog, Vera, SystemC, Specman E and Verilog. All the VIP's are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
