ARINC429 IP Core

ARINC429 IP Core

  • ARINC429 IP Core - Design IP Cores - ElectraIC

ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces. A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.

IP Core uses the AXI interface as an internal local bus. AXI interface is a 32-bit data bus which has 32-bit addressing and 32-bit read and write channels. IP supports 32 receive channel numbers and 16 transmit channel numbers.

The IP is designed to be compatible with DO-254. ARINC 429 IP is field approved.

 

SPECS

  • Supports ARINC 429 Specification
  • Configurable up to 32 Rx and 16 Tx Channels
  • Supports 12.5 kbit/s and 100kbit/s data rates
  • Contains 32-bit local data bus
  • Contains Individual and Circular buffer areas which have 1024-word depth for each channel
  • Supports single and periodic data transfer
  • Filter mechanism based on SDI, ESSM, Label of ARINC 429 data
  • Occurring of filter process in FPGA
  • Communication with CPU and external memory
  • Field Approved
  • DO-254 compliant

 

DELIVERABLES

  • Encrypted VHDL source code
  • ARINC 429 IP Core User Guide
  • Optional DO-254 Certification Data Package is available

 

LICENSING
The following licensing models are available:

  • Encrypted Netlist
  • Encrypted RTL
  • Encrypted RTL with DO-254 Certification Data Package

 

SUPPORT 
With the initial licensing, customers will receive the following services for the first year:

  • Half-day “IP Core First Time User Training”
  • Support during SOI meeting preparations is available with DO-254 Certification Data Package
  • IP Core update

 

DOCUMENTATION

ARINC429 IP Core Brochure

ARINC429 IP Core DataSheet

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