Design IP Cores

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Design IP Cores

MIL-STD-1553-IP Core

MIL-STD-1553 IP is an IP Core which implements the MIL-STD-1553B standard and provides a single or multi-functional interface between the host processor and the MIL-STD-1553 bus transceiver.
ARINC664 END SYSTEM IP Core

ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network.
ARINC664 SWITCH IP Core

ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network.
ARINC429 IP Core

ARINC 429 IP is an IP Core which implements ARINC 429 standard and IP contains Rx and Tx Processing Blocks, Controller Block, Internal Memory and External Memory Interfaces. A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.
AES IP Core

AES IP Cores is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in ”FIPS 197”.
AES GCM IP Core

AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197".
PRACH IP Suite

Optimize your 5G NR O-RAN Split 7.2X design with EIC cutting-edge PRACH Design and Verification Suite. This comprehensive suite includes an end-to-end MATLAB model, RTL implementation of the MATLAB model, and a robust verification environment for bit-exact simulation and testing. Ensure seamless integration and accelerate your development process with EIC 5G NR O-RAN compatible solution.
DRBG IP Core

DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'.
ECDSA IP Core

ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifications defined in 'FIPS 186'.
RSA IP Core

RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm specifications defined in 'FIPS 186'.
RSA Keygen IP Core

RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'.
SHA3 IP Core

SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'.
TRNG IP Core

TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'.
EAVS - ELECTRA IC Advanced Verification Suite

EAVS is a plug and play verification environment based on SystemVerilog and UVM. EAVS offers an environment to meet RISC-V/ARM based design verification needs in sectors such as automotive, defense, mobile, etc.

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