MIL-STD-1553 IP is an IP Core which implements the MIL-STD-1553B standard and provides a single or multi-functional interface between the host processor and the MIL-STD-1553 bus transceiver.
MIL-STD-1553 IP can function as a Bus Controller (BC), two separate Remote Terminal (RT) and a Bus Monitor (BM) simultaneously.
COMMON SPECS
64K bytes internal static RAM with RAM Error Detection/Correction option
16-bit time tag counters and clock sources for all terminals
64-Word Interrupt Log Buffer
Built-in and optional self-test for protocol logic, digital signal paths and internal RAM
Programmable 50/100 MHz Clock Frequency
DO-254 Compliant certification package
BUS CONTROLLER SPECS
Fully programmable Bus Controller
Bus Controller has 32-bit time count options
Programmable Status Set
Message Format Check
16 Condition Code for all opcode
64-Word General Purpose Queue for external BC Host
Programmable Inter-Message Gap Time (resolution 1us)
Programmable Message Timeout
REMOTE TERMINAL SPECS
Two independent Terminal Core
Programmable different buffer modes for all Subaddress
Subaddress-based illegal command declaration
Optional temporary buffer
BUS MONITOR SPECS
Basic Bus Monitor (BBM) records commands and data separately, with 16-bit or 48-bit time tagging
Optional support function for IRIG-106 data packets, including full packet headers and trailers
Bus Monitor has 32-bit and 48-bit time count options Message Filter Table
DOCUMENTATION
